1. Field of the Invention
The present invention relates to an apparatus comprising a clock control circuit which is suitable for synchronous control using high speed clock signals and a device using an internal clock signal synchronized to an external clock signal.
2. Related Art Statement
Recently, a computer system sometimes adopts a clock synchronous type memory, such as a synchronous DRAM, in order to fulfill the requirements for faster processing. A synchronous type memory is designed to use a clock, which is synchronized to a clock signal controlling a memory circuit, also within the memory.
When a delay occurs between a clock signal used within the memory (hereinafter referred to as an internal clock signal) and an external clock signal, such as a clock signal to control the memory circuit, and particularly when the operating speed is high, malfunction is apt to occur in a circuit even when the delay time is small.
Accordingly, a clock control circuit is provided in a semiconductor integrated circuit to synchronize an internal clock signal to an external clock signal.
FIG. 1 is a circuit diagram showing a related art on such a clock control circuit. FIG. 2 is a waveform diagram illustrating the theory. The circuit in FIG. 1 adopts an STBD (Synchronous Traced Backwards Delay) as a clock control circuit.
In FIG. 1, an external clock signal CK, shown in FIG. 2, is inputted to an input terminal 1. The period of the external clock signal CK is supposed to be xcfx84. This external clock signal CK is taken in through a receiver 2. The receiver 2 outputs an amplified clock signal CLK after waveform shaping of the external clock signal. When a delay time at the receiver 2 is D1, the clock signal CLK outputted from the receiver 2 becomes as shown in FIG. 2. A clock control circuit 20 is designed to generate a signal delayed by two periods of the external clock signal thereto.
In order to delay the clock signal CLK by (2xcfx84xe2x88x92D1), the clock control circuit 20, first, generates a pulse FCL, which rises after the time A from the rising timing of the clock signal CLK outputted from the receiver 2 as shown in FIG. 2. The time from the rising of this pulse FCL to the next rising of the clock signal CLK is, as shown in FIG. 2, the time xcex94 (=xcfx84xe2x88x92A). The clock control circuit 20 measures a time (xcfx84xe2x88x92A), and generates a next pulse RCL after the time 2(xcfx84xe2x88x92A) from the rising of the pulse FCL (see the pulse RCL in FIG. 2).
As shown in FIG. 2, the time from the rising of the pulse RCL to the rising of the next clock signal CLK is xcfx84xe2x88x92xcex94=xcfx84xe2x88x92(xcfx84xe2x88x92A)=A. Now, the time from the rising of the pulse RCL to the rising of the external dock signal CK to be inputted next is supposed to be D2. When D2 is a time as shown in FIG. 2, an internal clock CKxe2x80x2 (FIG. 2) is generated synchronizing to the external clock CK by being delayed by 2 periods to it.
As shown in FIG. 2, D2 is satisfactory so long as it is a value between D1 and A and has arelation of (D2+D1)=A. That is, when the time D2 is a delay time in an outputting stage, it means that an internal clock signal synchronized to the external clock signal can be generated by providing a delay circuit, which operates with the delay time A, the sum of the delay time D1 due to the receiver 2 and the delay time D2 in the outputting stage, and providing another delay circuit having a delay time of the time 2 (xcfx84xe2x88x92A).
Next, the operation of a circuit according to a related art will be described with reference to a block diagram shown in FIG. 1, waveform diagrams in FIGS. 3 and 4, and explanatory views shown in FIGS. 5 to 8. Particularly, the operation characteristics of an STBD to store the propagation condition of forward pulse and to control the propagation of rearward pulse corresponding to the stored data is described in detail.
The external clock signal CK having a period xcfx84 as shown in FIG. 3 is inputted to a receiver 2 via an input terminal 1, and CLK shown in FIG. 3 is outputted from the receiver 2. When a delay of the receiver 2 is D1, CLK is delayed by D1 to CK. When no clock control circuit is used, this delay D1 becomes, as it is, skew of the external clock signal and the internal clock signal. The more the external clock signal becomes high frequency and xcfx84 becomes smaller, the more the effect of this skew becomes great. The output signal CLK of the receiver 2 is inputted to an inverter 10, a control pulse generating circuit 9 and a delay monitor 3. At the control pulse generating circuit 9, the control pulse P as shown in FIG. 3 is generated. In a clock control circuit using an STBD, it is required to initialize all forward-pulse delay circuits before forward pulse is inputted to the first delay unit. By reason of this, a control pulse having a width narrower than the delay time A of a delay monitor 3 is generated, and control is carried out using this control pulse. The output signal FCL of the delay monitor 3 is delayed by A to CLK and inputted to a first forward-pulse delay circuit 5-1 of a forward-pulse delay line 5.
The N-th forward-pulse delay circuit forming a forward-pulse delay line outputs a logical value, which is similar to the output of the (Nxe2x88x921)th forward-pulse delay circuit, to the (N+1)th forward-pulse delay circuit when the control pulse P is xe2x80x9cLxe2x80x9d and outputs xe2x80x9cLxe2x80x9d to initialize a forward-pulse delay line 5 when P is xe2x80x9cHxe2x80x9d.
Output signals of forward-pulse delay circuits are also inputted to state-holding circuits. One of output signals of rearward-pulse delay circuits is also inputted to state-holding circuits. State-holding circuits have two states to take corresponding to signals inputted. The state-holding circuit takes the set state when P is xe2x80x9cLxe2x80x9d and forward pulse is propagated by the corresponding forward-pulse delay circuit. When P is xe2x80x9cHxe2x80x9d and rearward pulse is propagated by the corresponding rearward-pulse delay circuit, the state-holding circuit takes the reset state.
An output signal of the state-holding circuit is inputted to a rearward-pulse delay circuit. When the state-holding circuit to which the rearward-pulse delay circuit is connected is in the set state, the N-th rearward-pulse delay circuit inputs a logical value, which is similar to the output of the (N+1)th rearward-pulse delay circuit, to the (Nxe2x88x921)th rearward-pulse delay circuit. When the state-holding circuit connected to the rearward-pulse delay circuit is in the reset state, it outputs a logical value similar to the output of the receiver.
Next, the operation from the input of the forward pulse FCL to a forward-pulse delay line to the output of the output signal RCL from a rearward-pulse delay line is described in detail with reference to FIGS. 4 and 5 to 8. Each of FIGS. 5 to 8 shows the state of t0 to t3 in FIG. 4. Suppose that the delay time of a delay circuit is xcex94du, clock period is 10xcex94du, the pulse width is 5xcex94du, the width Axe2x80x2 of the control pulse P is 2xcex94du, the delay time A of the delay monitor is 3xcex94du. The set state is expressed with S and the reset state is expressed with R. The numerals marked on delay lines express the output of a delay circuit; xe2x80x9c1xe2x80x9d (=xe2x80x9cHxe2x80x9d) and xe2x80x9c0xe2x80x9d (=xe2x80x9cLxe2x80x9d) (xcex94du expresses a delay time per stage of delay circuits).
Now, suppose that, in the initial state at time t0, all state-holding circuits are in the reset state R. At this time, as an external clock signal has not been inputted, the output state of all forward-pulse delay circuits and rearward-pulse delay circuits is at xe2x80x9cLxe2x80x9d(FIG. 5).
When the forward pulse FCL is inputted to forward-pulse delay circuits, the forward pulse is then propagated by the forward-pulse delay line until the control pulse becomes xe2x80x9cHxe2x80x9d. As shown in FIG. 6, at time t1, when the forward pulse F1 has been propagated up to the 7th stage and the propagation is stopped due to P""S becoming xe2x80x9cHxe2x80x9d and then, the state-holding circuits in the first stage up to the 7th stage turn to the set state S, and the state-holding circuits in the 8th stage up to the last stage remain in the reset state R. At this time, CLK (=xe2x80x9cHxe2x80x9d) is inputted to the rearward-pulse delay circuit in the 7th stage to the last state, and the rising of rearward pulse is formed. On the other hand, as P is xe2x80x9cHxe2x80x9d the output of forward-pulse delay circuits becomes xe2x80x9cLxe2x80x9d and then the forward pulse F1 disappears after that.
At time t2, as P remains at xe2x80x9cHxe2x80x9d the rising of rearward pulse R1 is propagated to the preceding stage, changing state-holding circuits to the double-stage (=Axe2x80x2/xcex94du) reset state R (FIG. 7). This is for the purpose of generating rearward pulse from the stage where forward pulse is stopped even when forward pulse is not propagated up to the 7th stage because the period xcfx84 is shortened due to jitter.
Finally, when the input signal CLK for rearward-pulse delay lines becomes xe2x80x9cLxe2x80x9d at time t3, in the stages of state-holding circuits in the reset state, namely, in and after the 6th stage, the output of rearward-pulse delay circuits changes to xe2x80x9cLxe2x80x9d and the falling of rearward pulse is formed (FIG. 8).
Attention is required to a fact that the pulse width of rearward pulse becomes narrow by the number of stages of state-holding circuits which have been reset as an anti-jitter measure. After this, by repeating the operation in FIGS. 5 to 8, a signal RCL being delayed by xcfx84xe2x88x92A=7xcex94du from the rising of the output signal CLK of a receiver can be outputted.
The output signal RCL of rearward-pulse delay lines is inputted to an output buffer 8 and outputted, as an internal clock signal CKxe2x80x2 after being delayed by D2 to the rearward pulse RCL.
The delay time xcex94 total of the internal clock signal CKxe2x80x2 to the external clock signal CK is:
xcex94total=D1+A+2(xcfx84xe2x88x92A)+D2
When the delay time of the receiver 2 and the output buffer 8 is known and A=D1+D2, the following equation holds good:
xcex94total=D1+A+2(xcfx84xe2x88x92A)+D2=D1+(D1+D2)+2(xcfx84xe2x88x92(D1+D2))+D2=2(D1+D2)+2xcfx84xe2x88x922(D1+D2)=2xcfx84
As xcex94 total becomes 2xcfx84, consequently, the external clock signal and the internal clock signal are synchronized.
However, in the example of a related art in FIG. 1, two problems arise: one problem is that, when forward pulse is propagated to the last stage of the forward-pulse delay line 5, a time when an internal clock signal is not generated satisfactorily lasts long; and the other is that it becomes impossible to synchronize the external clock signal to the internal clock signal when the duty cycle of the external clock signal is large.
FIGS. 9A and 9B are explanatory views illustrating problems which arise when forward pulse is propagated up to the last stage. FIG. 9A shows a state where the operation to generate clock signals is broken off, and FIG. 9B shows a state where the operation to generate clock signals is resumed.
Application of an STBD to a synchronous DRAM is considered. In this case, an internal clock signal is a clock signal used in a memory circuit, and an external clock signal is a clock signal to control the memory circuit. In such a synchronous DRAM, when a fast external clock signal is always taken in, the electric power consumption extremely increases. To cope with this, a mode not to take in an external clock signal when necessary (hereinafter referred to as power save mode) is sometimes adopted by suspending the generation of external clock signal temporarily or turning off the receiver 2.
As a result of adoption of such a power save mode, the output of the receiver 2 may be broken off in the middle while the forward pulse FCL is being propagated by the forward-pulse delay line 5. In an STBD, as described above, the forward pulse FCL, which was inputted to the forward-pulse delay line 5 immediately before the power save mode""s being turned on, keeps being propagated by the forward-pulse delay line 5 until the control pulse P becomes xe2x80x9cHxe2x80x9d.
However, when supply of clock signals to synchronous circuits is stopped, as generation of the control signal P to stop propagation of forward pulse ceases. As shown in FIG. 9A, forward pulse corresponding to the clock signal immediately before the supply of clock signal is stopped is propagated up to the last stage of delay line. Thus, all state-holding circuits turn to the set state. Besides, as CLK is inputted to the rearward-pulse delay circuit in the last stage, when the supply of clock signals resumed, as shown in FIG. 9B, rearward pulse is not generated from the 7th stage where the propagation of forward pulse was stopped.
FIG. 10 is an explanatory view illustrating the second problem.
As shown in FIG. 10, the duty cycle of an external clock signal exceeds 50%. FIG. 10 shows a state where a first rearward pulse R1 is propagated by rearward pulse delay lines, the propagation of a second forward pulse F2 is stopped, and the rising of a second rearward pulse R2 is formed.
In this state, similarly to FIG. 6. the control pulse P is xe2x80x9cHxe2x80x9d and at this time, the state-holding circuits in the first stage up to 5th stage where rearward pulse R1 is propagated are changed to the reset state R as an anti-jitter measure. When rearward pulse R2 is propagated to the 5th stage, as forward pulse F3 has not reached there, state-holding circuits remain in the reset state R, and the propagation of R2 is stopped. That is, when the time Tb required by rearward pulse to reach the 5th stage from its generation is larger than the time Tf required by forward pulse F3 to reach the 5th stage from the generation of rearward pulse, propagation is stopped for the time Tfxe2x88x92Tb.
As this stopped time is added to the time to generate an internal clock signal, synchronization to an external clock signal can not be established.
In FIG. 10, the pulse width d of the rearward pulse R1 is supposed to be the same as the pulse width of CLK. As shown in FIG. 7, the pulse width of rearward pulse is changed by x and y. The problem shown in FIG. 10 also arises when a pulse width is changed in such a manner.
In order to have rearward pulse propagated by the rearward-pulse delay line 7, as state-holding circuits have to be kept in the set state, the forward pulse F2 have to be propagated to the N-th stage before the rearward pulse R1 is propagated to the N-th stage. Namely, as obvious in FIG. 10, the condition for the rearward pulse R1 to be propagated in a preceding stage of the N-th stage is expressed with the following equation:
d less than (xcfx84xe2x88x92A)xe2x88x92(dxe2x88x92A)=xcfx84xe2x88x92d
Accordingly, d less than xcfx84/2 is the necessary condition.
In this condition, too, the widths of the pulse width of CLK and that of rearward pulse are considered the same.
Thus, in a related art on a clock control circuit described above, a problem that a time when an internal clock signal is not generated lasts long arises when forward pulse is propagated up to the last stage of forward-pulse delay lines. Besides, there is another problem that, when the duty cycle of an external clock signal is large synchronization between the external clock signal and an internal clock signal can not be established.
An object of the present invention is to provide an apparatus comprising a clock control circuit which is able to prevent delays from arising during the generation of a next internal clock signal even when the output of a receiver to take in an external clock signal is temporarily stopped and a device using an internal clock signal synchronized to an external clock signal.
Another object of the pre sent invention is to provide an apparatus comprising a clock control circuit which is able to establish synchronization between an external clock signal and an internal clock signal even when the duty of the external clock signal is heavy and a device using an internal clock signal synchronized to an external clock signal.
A clock control circuit according to the present invention comprises a forward-pulse delay line which is configured by cascading a plurality of stages of forward-pulse delay circuits to propagate inputted signals with a predetermined delay time so as to delay said inputted signals, and delays forward pulse corresponding to a second clock signal obtained by delaying a first clock signal, which is obtained by delaying an external clock signal by a first delay time, by a second delay time corresponding to the difference between the period of said first clock signal and said first delay time, a rearward-pulse delay line which is configured by cascading a plurality of stages of rearward-pulse delay circuits to propagate inputted signals with a predetermined delay time so as to delay said inputted signals, and, by being set to the reset state of a stage corresponding to the stage of the forward-pulse delay line where said forward pulse is propagated after said second delay time from the start of propagation of said forward pulse by said forward-pulse delay line and also by being set to the set state of stages corresponding to the first stage up to the stage of the forward-pulse delay line where said forward pulse is propagated, propagates rearward pulse, which is generated in said stage in the reset state by taking in said first clock signal selectively, by said stages in the set state and outputs said rearward pulse from the first stage, a state-holding device which is configured with a number of stages corresponding to the number of stages of said forward-pulse delay line and rearward-pulse delay line, and, by turning stages corresponding to the stages of the forward-pulse delay line where said forward pulse is propagated during the one polarity pulse duration of said first clock signal to the set state and also by turning a stage corresponding to the stage where said rearward pulse is propagated only for a predetermined time from the edge of said first clock signal to the reset state, controls propagation of said rearward pulse by said rearward-pulse delay line, and a state-holding circuit initializing device which initializes said state-holding device to the reset state when said state-holding circuit initializing device detects that said first clock signal is not generated.
A clock control circuit according to the present invention comprises a forward-pulse delay line which is configured by cascading a plurality of stages of forward-pulse delay circuits to propagate inputted signals with a predetermined delay time so as to delay said inputted signals, and delays forward pulse corresponding to a second clock signal obtained by delaying a first clock signal, which is obtained by delaying an external clock signal by a first delay time, by a second delay time during the one polarity pulse duration of said first clock signal, a rearward-pulse delay line which is configured by cascading a plurality of stages of rearward-pulse delay circuits to propagate inputted signals with a predetermined delay time so as to delay said inputted signals, and, by being set to the reset state of a stage corresponding to the stage where said forward pulse is propagated after said second delay time and also by being set to the set state of stages corresponding to the first stage up to the stage where said forward pulse is propagated, propagates rearward pulse, which is generated in said stage in the reset state by taking in said first clock signal selectively, by said stage in the set state and outputs said rearward pulse from the first stage, a state-holding device which is configured with a number of stages corresponding to the number of stages of said forward-pulse delay line and rearward-pulse delay line, and, by turning stages corresponding to the stages where said forward pulse is propagated during the one polarity pulse duration of said first clock signal to the set state and also by turning stages corresponding to the stages where said rearward pulse is propagated only for a first time from the edge of said first clock signal to the reset state, controls propagation of said rearward pulse by said rearward-pulse delay line, and a state-holding circuit control device which generates control signals to set said first time corresponding to the rearward pulse outputted from said rearward-pulse delay line.
A clock control circuit according to the present invention comprises a forward-pulse delay line which is configured by cascading a plurality of stages of forward-pulse delay circuits to propagate inputted signals with a predetermined delay time so as to delay said inputted signals, and delays forward pulse corresponding to a second clock signal obtained by delaying a first clock signal, which is obtained by delaying an external clock signal by a first delay time, by a second delay time during the one polarity pulse duration of said first clock signal, a rearward-pulse delay line which is configured by cascading a plurality of stages of rearward-pulse delay circuits to propagate inputted signals with a predetermined delay time so as to delay said inputted signals, and, by being set to the reset state of stages corresponding to the stages where said forward pulse is propagated after said second delay time and also by being set to the set state of stages corresponding to the first stage up to the stage where said forward pulse is propagated, propagates rearward pulse, which is generated in said stage in the reset state by taking in said first clock signal selectively, by said stage in the set state and outputs said rearward pulse from the first stage, a state-holding device which is configured with a number of stages corresponding to the number of stages of said forward-pulse delay line and rearward-pulse delay line, and by turning stages corresponding to the stages where said forward pulse is propagated during the one polarity pulse duration of said first clock signal to the set state and also by turning stages corresponding to the stages where said rearward pulse is propagated only for a first time from the edge of said first clock signal to the reset state, controls propagation of said rearward pulse by said rearward-pulse delay line, a state-holding circuit control device which generates control signals to set said first time according to the rearward pulse outputted from said rearward-pulse delay line, and a forward-pulse adjusting device to adjust the pulse width of said forward pulse corresponding to the rearward pulse outputted from said rearward-pulse delay line and said forward pulse.
An apparatus according to the present invention comprises a first device which operates corresponding to an external clock signal, a transmission line to transmit data, a clock control circuit having a forward-pulse delay line which is configured by cascading a plurality of stages of forward-pulse delay circuit to propagate inputted signals with a predetermined delay time so as to delay said inputted signals, and delays forward pulse corresponding to a second clock signal obtained by delaying by a first delay time a first clock signal, which is obtained by delaying said external clock signal, by a second delay time during the one polarity pulse duration of said first clock signal, a rearward-pulse delay line configured by cascading a plurality of stages of rearward-pulse delay circuit to propagate inputted signals with a predetermined delay time so as to delay said inputted signals, and, by being set to the reset state of stages corresponding to the stages where said forward pulse is propagated after said second delay time and also by being set to the set state of stages corresponding to the first stage up to the stage where said forward pulse is propagated, propagates rearward pulse, which is generated in said stage in the reset state by taking in said first clock signal selectively, by said stage in the set state and outputs said rearward pulse from the first stage, a state-holding device which is configured with a number of stages corresponding to the number of stages of said forward-pulse delay line and rearward-pulse delay line, and, by turning stages corresponding to the stages where said forward pulse is propagated during the one polarity pulse duration of said first clock signal to the set state and also by turning stages corresponding to the stages where said rearward pulse is propagated only for a first time from the edge of said first clock signal to the reset state, controls propagation of said rearward pulse by said rearward-pulse delay line, a state-holding circuit control device to generate control signals to set said first time corresponding to rearward pulse outputted from said rearward-pulse delay line, and an output device to output an internal clock signal obtained by delaying said rearward pulse by a third delay time, and a device which uses an internal clock signal synchronized to an external clock signal comprising a second device to perform predetermined processes using said internal clock signal and to transmit the processed result to said transmission line.
Other features and advantages of the present invention will become apparent enough from the following description.